InSy Rostock

Processors that do one thing extremely well. We design accelerators that fit their task, from reconfigurable logic to our own silicon, and leave out everything a general-purpose processor carries along.

An accelerator is only as good as its place in the whole. We integrate CPUs, FPGAs and specialised cores into one system in which data, scheduling and security are designed together.

Neural networks are reshaped before they reach the chip: recoded, quantised, searched for the right structure. Our Computation Coding is one example. Model and hardware are designed together, so efficiency comes from both sides.

Bandwidth, hierarchy and data layout decide whether a processor computes or waits. We design memory paths so that data arrives in parallel and journeys stay short, from on-chip buffers to high-bandwidth memory.

Non-volatile devices such as memristive RRAM keep their state without power, store several bits per cell and tolerate radiation. We turn these properties into architectures and take their flaws seriously: variability, drift and temperature are modelled, not ignored.

Moving data costs more than computing with it. So we bring the computation to where the data lives: next to the memory, into its periphery, or into the cells themselves. A principle for any technology, and a natural fit for memristive arrays.

A system exists in software long before it exists in silicon. Virtual prototypes run real software on an architecture that is still an idea, measure what it would cost, and make alternatives comparable early.

How fast, how much energy, how accurate? We build models of devices, circuits and architectures that answer this reliably: analytical, simulated or learned from measurements. As abstract as possible, as precise as necessary.

Good architectures should be reproducible, not handmade once. Generators, emulation on FPGAs and a growing library of reusable building blocks turn design decisions into hardware, again and again.

Our work should be useful: for climate and energy, health, participation and fairness, and for technical progress that is handled responsibly.

We do not develop or use knowledge and technology to harm people, society, the environment or civil infrastructure. Our research serves neither destruction nor the escalation of conflicts.

We design technical systems to be sparing with energy and resources. Energy-efficient computer architectures are our direct contribution.

Origin, age, gender, identity, orientation, background, language, belief or life path play no role in belonging here. Discrimination is not tolerated – whether open, hidden or built into structures.

Honest, careful and reproducible, following the DFG guidelines. We are open about uncertainty, credit the contributions of others fairly, and both voice and accept criticism.

Wherever possible, we publish not only papers but artefacts that others can reproduce and build on – code, models and hardware descriptions.

The foundations: from gates and flip-flops to the first processor. For many students the first contact with the chair.

Describing, simulating and synthesising hardware – the craft behind every accelerator.

From hardware description to a manufacturable integrated circuit.

Processor microarchitecture in depth – pipelines, memory hierarchies and your own design projects.

How neural networks run efficiently on hardware: accelerators, data flows, quantisation and the limits set by memory.

Topics come from the three research groups. A topic can be reserved for a limited time while you shape it together with your supervisor.