Compute-Centric
Domain-specific, heterogeneous and reconfigurable architectures
How computing becomes fast and frugal. Architectures tailored to their task, accelerators and their interplay in the whole system, on FPGAs and in our own silicon.
Topics
Hardware accelerators.
Processors that do one thing extremely well. We design accelerators that fit their task, from reconfigurable logic to our own silicon, and leave out everything a general-purpose processor carries along.
Heterogeneous systems.
An accelerator is only as good as its place in the whole. We integrate CPUs, FPGAs and specialised cores into one system in which data, scheduling and security are designed together.
AI optimisation for hardware.
Neural networks are reshaped before they reach the chip: recoded, quantised, searched for the right structure. Our Computation Coding is one example. Model and hardware are designed together, so efficiency comes from both sides.
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Selected projects
Funded projects the group works in.
- Computation Coding DFG
Foundations of Computation Coding: recoding linear maps so that neural networks need far fewer operations.
- KERE BMFTR
Combining Computation Coding with tensor trains for compact, efficient inference.
- ELAINE B06 DFG
RRAM and Computation Coding for electrically active implants, within the collaborative research centre ELAINE.
- PICANT-BOS BMWK
Energy-efficient edge computing for public-safety radio.
- FERC-ID DAAD
Architectures for predictive maintenance of drone drives, with international partners.
Group lead
Members
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Amir Hosein YazdanpanaResearch Associate - Babak RooholahiResearch Associate